top Project Status (09/26/2010 - 15:44:52)
Project File: template.xise Parser Errors: No Errors
Module Name: top Implementation State: Fitted
Target Device: xc2c256-7TQ144
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSo 26. Sep 16:02:01 2010000
Translation ReportCurrentSo 26. Sep 16:02:08 2010000
CPLD Fitter Report (Text)CurrentSo 26. Sep 16:02:11 201001 Warning (1 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 09/26/2010 - 16:39:35