Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version2086221
date_generatedWed Jan 17 15:56:33 2018 os_platformLIN64
product_versionVivado v2017.4 (64-bit) project_id51f70ea68ca34942b1bd52621b7d009b
project_iteration1 random_idc7baddacdecf5d218cce7e86d498aa75
registration_id177802993_0_0_303 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-4670K CPU @ 3.40GHz cpu_speed3784.492 MHz
os_nameUbuntu os_releaseUbuntu 16.04.3 LTS
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_apply=1 basedialog_cancel=1 basedialog_ok=6 constraintschooserpanel_add_existing_or_create_new_constraints=1
constraintschooserpanel_add_files=1 filesetpanel_file_set_panel_tree=3 flownavigatortreepanel_flow_navigator_tree=1 mainmenumgr_file=2
maintoolbarmgr_run=2 msgtreepanel_message_view_tree=3 msgview_critical_warnings=1 msgview_warning_messages=1
numjobschooser_number_of_jobs=1 pacommandnames_add_sources=1 pacommandnames_goto_netlist_design=1 pacommandnames_new_project=1
pacommandnames_run_bitgen=1 pacommandnames_run_implementation=2 pacommandnames_run_synthesis=1 partchooser_boards=3
projectnamechooser_project_name=1 rungadget_show_error_and_critical_warning_messages=2 settingsdialog_project_tree=2 srcchooserpanel_add_directories=1
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2 srcchooserpanel_add_or_create_source_file=1 srcchooserpanel_simulator_language=2
java_command_handlers
addsources=1 newproject=1 runbitgen=1 runimplementation=2
runsynthesis=1 showview=1 toolssettings=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=2 export_simulation_ies=2
export_simulation_modelsim=2 export_simulation_questa=2 export_simulation_riviera=2 export_simulation_vcs=2
export_simulation_xsim=2 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=9 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 carry4=17 dsp48e1=1 fdre=91
fdse=8 gnd=5 ibuf=11 lut1=2
lut2=41 lut3=35 lut4=13 lut5=58
lut6=81 obuf=28 vcc=4 xadc=1
pre_unisim_transformation
bufg=1 carry4=17 dsp48e1=1 fdre=91
fdse=8 gnd=5 ibuf=11 lut1=2
lut2=41 lut3=35 lut4=13 lut5=58
lut6=81 obuf=28 vcc=4 xadc=1

ip_statistics
xadc_wiz_v3_0/1
channel_averaging=None component_name=xadc_wiz_0 core_container=NA dclk_frequency=100
enable_axi=false enable_axi4stream=false enable_busy=true enable_convst=false
enable_convstclk=false enable_dclk=true enable_drp=true enable_eoc=true
enable_eos=true enable_vbram_alaram=false enable_vccaux_alaram=falseenable_vccpaux_alaram=false enable_vccddro_alaram=false
enable_vccint_alaram=false enable_vccpint_alaram=false iptotal=1 ot_alaram=false
sequencer_mode=on startup_channel_selection=contineous_sequence timing_mode=continuous user_temp_alaram=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 dpip-1=1 dpop-1=1 dpop-2=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=1 dsps_available=90 dsps_fixed=0 dsps_used=1
dsps_util_percentage=1.11
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=17
dsp48e1_functional_category=Block Arithmetic dsp48e1_used=1 fdre_functional_category=Flop & Latch fdre_used=91
fdse_functional_category=Flop & Latch fdse_used=8 ibuf_functional_category=IO ibuf_used=11
lut1_functional_category=LUT lut1_used=2 lut2_functional_category=LUT lut2_used=41
lut3_functional_category=LUT lut3_used=35 lut4_functional_category=LUT lut4_used=13
lut5_functional_category=LUT lut5_used=58 lut6_functional_category=LUT lut6_used=81
obuf_functional_category=IO obuf_used=28 xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=216 lut_as_logic_util_percentage=1.04
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=99 register_as_flip_flop_util_percentage=0.24
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=216 slice_luts_util_percentage=1.04
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=99 slice_registers_util_percentage=0.24
fully_used_lut_ff_pairs_fixed=0.24 fully_used_lut_ff_pairs_used=2 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=216 lut_as_logic_util_percentage=1.04
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=83
lut_ff_pairs_with_one_unused_lut_output_fixed=83 lut_ff_pairs_with_one_unused_lut_output_used=80 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=86 lut_flip_flop_pairs_util_percentage=0.41 slice_available=8150 slice_fixed=0
slice_used=82 slice_util_percentage=1.01 slicel_fixed=0 slicel_used=44
slicem_fixed=0 slicem_used=38 unique_control_sets_used=6 using_o5_and_o6_fixed=6
using_o5_and_o6_used=14 using_o5_output_only_fixed=14 using_o5_output_only_used=4 using_o6_output_only_fixed=4
using_o6_output_only_used=198
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=1 xadc_used=1 xadc_util_percentage=100.00

router
usage
actual_expansions=411442 bogomips=6796 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=6
dsp=1 effort=2 estimated_expansions=408000 ff=99
global_clocks=1 high_fanout_nets=0 iob=39 lut=228
movable_instances=398 nets=508 pins=2660 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=4 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=XADCdemo -verilog_define=default::[not_specified]
usage
elapsed=00:00:35s hls_ip=0 memory_gain=520.160MB memory_peak=1682.633MB